Origins of Dennard Scaling

• Robert Dennard at IBM invented 1 capacitor, 1 transistor DRAM concept in early 1970s
• IBM research program goal: cut memory costs to $0.00001 per bit (hundreds of times improvement)
• Required shrinking MOSFET transistor to 1 micrometer (from 5 micrometers)
• Team discovered scaling all transistor dimensions + voltage by same factor K maintained performance
• Hwa-Nien Yu built 1-micrometer transistors that worked almost exactly the same
• Electric field strength = voltage/channel distance remains constant when both scale equally

Key Benefits Discovered

• Faster switching: charge carriers travel shorter distance between source/drain
• Lower power consumption: smaller voltage reduces power draw
• Dynamic switching power formula: function of capacitance, supply voltage squared, switching frequency
• Scaling enables higher switching frequency without increasing power
• Example: 10 transistors → 20 transistors with same total power consumption

Publication and Recognition

• First published 1972 at International Electron Devices Meeting
• Audience laughed at scaling gate oxide from 100nm to 20nm
• 1974 paper "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions" in IEEE Journal
• Became journal's most cited article
• Introduced dimensionless scaling factor "K" in table format
• Established "Dennard Scaling" or "Dennard's Law"

CMOS Era Integration

• Combined with Complementary Metal Oxide Semiconductors (CMOS)
• CMOS: combination of N-type MOS (electrons) and P-type MOS (electron holes)
• 10x scaling = 10x faster performance
• Historical problem: industry standard 5V supply voltage too high for scaling
• High voltage damaged gates when channel length shrank
• Early 1990s: industry roadmap reduced voltages from 5V to 1.2-1V
• Enabled golden age of Dennard Scaling for CMOS

Breakdown: Short Channel Effects

• Late 1990s: Intel CPUs shrank rapidly with 193nm DUV lithography
• Gate oxides reached ~5nm thickness
• Channel lengths ~25nm with doping limitations
• Sub-threshold leakage became major issue
  • Residual current below threshold voltage
  • Lower threshold voltage = worse leakage
  • 90nm node: leakage = 30% of total power draw
  • Heat increases leakage (2% per Celsius degree)
  • Transistor temperatures 4.5x higher than 350nm era

The Power Wall

• 2003 roadmap projected 53 GHz single-core frequencies by 2018
• Reality: frequencies topped out at 4 GHz per core since 2006
• Heat and power constraints created "Power Wall"

Multicore Response

• First commercial multicore: IBM Power4 (2001)
• AMD dual-core Opteron (2004)
• Intel Pentium D (2005)
• AMD VP Dirk Meyer: "little or no increase in power consumption or heat dissipation"
• Software unpreparedness: most programs not parallelized
• Herb Sutter's "Free Lunch is Over" (2005): end of automatic performance gains
• Amdahl's Law limited parallelization speedup
• Years required for software adaptation

Dark Silicon Concept

• Early 2010s: Hadi Esmaeilzadeh (UC San Diego) introduced "Dark Silicon"
• Moore's Law continues: 2x transistors every 2-3 years
• Power/heat limits require shutting down significant chip percentages
• Predictions: up to 93% of chip "dark" at times
• Challenge: smart resource allocation to avoid hot spots

Navigation Strategies

• New innovations beyond Dennard Scaling:
  • High-K metal gate
  • Silicon On Insulator (SOI)
  • FinFET
  • Future: nanosheet technology
• System on Chip (SoC) paradigm: specialized sections for different functions
• "Dimming" instead of shutdown: underclocking, cache conversion
• ARM Big.Little: A15 high-performance cores switch to A7 efficient cores at thermal limits
• Mobile boom (2010s): power premium drove efficiency focus
• Deep learning era (2012): GPUs leveraged parallelism and large core counts

Industry Impact Analysis

• Bob Colwell (Intel Chief Architect 1992-2000) saw writing on wall
• Left Intel partly due to disagreement over Pentium 4 follow-up strategy
• Refused to work on Prescott: "technologically finished, dead end"
• Intel's focus on execution speed led to unsustainable gate length shrinking
• End of Dennard Scaling changed industry control dynamics forever
• Enabled diversified computing forms beyond single-thread CPU-centric paradigm