DARPA Investment and Open Source EDA Background

• 2018: DARPA announced $100M investment in open source tools and silicon blocks for SOCs/circuit boards
• Goal: bend cost curve of modern semiconductor silicon manufacturing
• Open source EDA community existed for decades but fell behind commercial industry due to leading-edge fabrication difficulty
• RISC-V open source hardware innovations casting light on open source EDA space

Semiconductor Design Cost and Stagnancy Challenges

• Designing semiconductors (even non-5nm) is difficult and expensive
• IP licensing costs major barrier:
  • ISA (Instruction Set Architecture) controlled by Intel, ARM
  • Developer unwillingness to pay licensing costs drove RISC-V adoption
• EDA tool costs significant:
  • Three major EDA companies invest 25% revenues in R&D
  • Primary audience: major enterprise clients (NVIDIA, Apple, Qualcomm)
  • Not suited for smaller teams making $10 IoT chips or specific design requirements
• Proprietary IP licenses reduce value of sharing research
• Students, teachers, enthusiasts lack access to expensive/NDA-required tools
• Creates talent shortages and blocks hardware community collaboration

Historical Open Source EDA Tools

• Tools existed since 1980s, predating Linux
• SPICE:
  • General purpose circuit simulation from early 1970s at UC Berkeley
  • Used to teach chip designers
  • Practical, reliable, easy to use, free
  • Name became verb ("let's spice that")
• Magic:
  • Interactive VLSI circuit layout system
  • Based on Mead-Conway design style
  • Simple rules for designing basic cells in hierarchical structure
• VIS (Verification Interacting with Synthesis):
  • Automatic formal verification tool
• QFlow: End-to-end software flow from Verilog source to physical layout for fabrication

DARPA Open Road Project

• Launched June 2018 with DARPA funding
• Goal: RTL (Verilog) to final manufacturable layout in 24 hours, no additional people needed
• Version 1.0 integrated ~20 tools into single app
• Replace tool: Floor planner component
• Successes:
  • Tape outs for 12nm SOC
  • Passed verification checks for TSMC 65nm low power
  • Global Foundries 12nm low power process
• Features graphical user interface (GUI)

Additional Open Source Projects

• Chisel:
  • Alternative to Verilog/VHDL
  • Based on Scala, blends software architectures
  • More modern feel
  • Used in Berkeley's Rocket Chip (RISC-V chip generator)
• OpenRAM:
  • Addresses SRAM (Static Random Access Memory) design
  • Every SOC has embedded memory component
  • Memory designs critical in chip design
  • Advanced nodes make memory particularly tricky
  • Provides standard for researchers

Process Design Kit (PDK) Roadblock

• PDK = set of design rules, physical limitations, simulators, IP libraries, design rule checkers
• Provided by foundries (TSMC, Global Foundries) to fabless design companies
• PDK and EDA software tightly coupled
• Foundries incentivized to work with few companies for simplicity
• Lack of integrated PDK left many open source EDA efforts half-hearted
• TSMC's advanced PDKs (N5, N3) only available to top customers like Apple
• Even older nodes require NDA signing

Skywater Technologies Open PDK Initiative

• Skywater partnered with Google to launch PDK for 130nm node
• Freely available on GitHub
• Allows scrutinization and improvement of PDK
• Announcement livestreamed on YouTube June 2020:
  • 10,000 views first week
  • ~23,700 views total
• Other projects: Academic-oriented Free PDK, OpenRoad's ASAP7 (7nm FinFET research PDK)
• Academic PDKs not for commercial use

Open Source EDA Philosophy and Future

• Won't achieve "ultimate quality of results" like commercial tools
• Market-leading semiconductor design too optimized for open source to match
• Focus on "ultimate ease of use" instead
• Not every chip needs to be 5nm monster
• Goal: democratize hardware design for teams worldwide
• Enable cool stuff creation and contribution to open source hardware
• Google doing significant work in open source hardware design space